Unit 1
Microprocessor is a CPU on a single IC containing millions of very small components including
all the above
8008 is _____ bit microprocessor , invented in _____ year
8 bit , 1972
—Based on the application of the processor, microprocessor are classified as
all the above
word and double word indicates
16,32
Identification number for memory locations indicates
address
square wave used to synchronize various devices in Îœp indicates _______
clock cycle
Memory Capacity = 2^n , where n indicates
address lines
—The 8086 architecture illustrates the implementation of ___________pipelining in instruction execution
two-stage
EU-takes the instruction from___________ and executes it
BIU
8086 has _________ operating modes
2
address bus and data bus capability of 8086 processor is
20,16
8086 requires one phase clock with a _____ duty cycle
33%
Clock frequency OF 8086 microprocessor is _______
5 MHz
Segment register of 8086 are
CS,DS,ES & SS
8086 has ____________ instruction queue
6 byte
__________ physical memory is divided into four segments , in 8086
1 MB
Each segment has memory space of __________
64 KB
The part of memory from where BIU is currently fetching instruction code bytes is the function of _______ segement
code
which segment register is Used for storing data values to be used in the program
extra and data
A section of memory set aside to store addresses and data while a subprogram executes is the function of _______ segement
stack
BIU stores these ________ bytes in a _______ register called Instruction Queue
pre-fetched , FIFO
main components of EU are
all the above
EU has ______ general purpose registers it Can be individually used for storing _________bit data
4,8
The valid register pairs are –
AX, BX, CX, DX
Which register , Provides indirect access to data in stack register
base pointer
Which unit , Generates timing and control signals to perform the internal operations of the microprocessor
EU
EU has a _________ bit ALU
16 bit
flag register is also called as ___
PSW
flag register has _____ control flags and _____ status flags
3,6
___________ Specifies a rule for instruction before the operand is actually executed.
addressing mode
Operand addressing has ______ number of bits
20 bit
__________ specifies the operation to be performed in an instruction
opcode
_________ provides the data required for operation
operand
size of integer , short integer , long integer is
16,8,32
group of bytes or group of words are called as ______________
strings
there are ________ number of addressing modes in 8086
8
MOV CX,[BX] is an example for ____________ addressing mode
register indirect
MOV CL,[1200H] is an example for ____________ addressing mode
direct
__________ are the symbolic codes for either instructions or commands to perform a particular function
mnemonics
___________ instruction Copies data from main memory in to register
load
__________instruction Copies data from register in to main memory
store
rotate through carry left is the full form of _________
RCL
_________ instruction stop the fetching and execution of the instructions
HLT
__________is connected to an external bus controller device, which then prevents any other processor from taking over the system
LOCK
LENGTH and OFFSET belongs to which directives
both b & c
__________ assembler used in instructions to assign a specific type to a variable or a label
PTR
Modular programming requires extra ____________
time and memory
__________________is the repeatedly appearing small group of instructions
macro
__________ number of interrupts are divided in to 3 groups
256
Intel introduced the concept of memory segmentation ________________ microprocessor
8086
UNIT 2
The signals of 8086 are grouped ____ categories
3
During 1st clock cycle _________ available on the (AD0-AD15).
either A or B
During remaining clock cycles other than 1st clock cycle , (AD0-AD15) lines contains _______
16 bit data
High order address bus are multiplexed with ______
status signals
00 combination of S3 and S4 in status signals of 8086 indicates ______ segment register
ES
11 combination of S3 and S4 in status signals of 8086 indicates ______ segment register
DS
TEST pin is used to check the status of math co-processor
8087
Reset, must be active for at least________clock cycles to reset the microprocessor.
four
INTR indicates
interrupt request signal
Address Latch Enable – indicates valid ________ is available on the address bus
16 bit address
which signal decides the direction of data flow through the transceiver
DT/R
when DMA controller needs to use Address / Data bus , it sends a request to the CPU through this pin.
both A & B
Pin 24 & 25 – QS1 & QS0 – provides the status of ________ .
instruction queue
Pin 24 & 25 – QS1 & QS0 , Can be used by _________devices to know the_________ status of the queue
external , internal
1 & 0 combination of QS1 and QS0 indicates _____ operation
empty queue
When this pin goes low , all interrupts are masked and HOLD request is not granted.
LOCK
Processing unit issues control signals required by memory and i/o devices through the pins __________
24-31
The control signals in minimum mode are generated_________
internally
clock generator chip set number is ________
8284
address latch chip set number is ____________
8282
Transceiver chip set number is ___________
8286
The only difference in MIN and MAX mode lies in the ___________ used and the available control and advanced signals.
status signals
The time required by the microprocessor to complete an operation of accessing memory or input/output devices is called __________
machine cycle
A bus cycle takes , ______ states
4 T
EU and BIU will be working _________
asynchronously
The only other instant EU waits for BIU is when BIU is executing ___________ access for EU.
data memory
in MAX mode , the status signals will be active for ______ cycle and inactive for next ______ cycles
2 T , 2 T
Based on the status signals these operations will be executed
all the above
A set of __________used for communicating the information between the components is called Bus
conductors
If a bus connects two minor components within a major components, it is called as ____________
internal bus
If a bus connects two major components, like CPU and an interface, it is called as _____________
external bus
Drivers and receivers are used when several interfaces are connected to ____________
address and data bus
Latches are used to___________time multiplexed signals
separate
_______ are used for synchronizing the signals
both A & B
The 8086 can be interfaced to 8 – and 16-bit I/O devices using either
all the above
The standard I/O uses the instructions IN and OUT and is capable of providing_________ of I/O ports
64K bytes
In 8086, all programmed communications with the I/O ports is done by the________ instructions
IN and OUT
What are all belongs to I/O contents
all the above
In ______ operation The CPU issues a command then waits for I/O operations to be complete.
programmed I/O
The CPU, while waiting, must repeatedly check the ________ of the I/O module, and this process is known as _________
status , polling
If interrupt occurs , then Pushing the current content of ___________ onto the stack will takes place
all the above
The identification of the device requesting service can be done by__________
both A & B
Polling is a __________ mechanism, by which devices are serviced in sequential order
synchronous
Direct Memory Access needs a special hardware called ______
DMAC
Maximum mode of 8086 is designed to implement __________basic multiprocessor configurations:
3
The coprocessor shares _________ with 8086 microprocessor
all the above
Coprocessor and the processor is connected via __________ pin
all the above
Communication between the host and the independent processor is done through ________
memory space.
It consists of the number of modules of the microprocessor based systems , which are connected through a common _________
system bus.
80186 has the address and data bus capability of
16,20
UNIT 3
8086 has ______address lines
20
Memory capacity of 8086 is ________.
220= 1MB
The memory addresses are ranginging from ____________.
00000 to FFFFF H
Memory is divided into ____________ banks.
2
Each memroy loacation strores ____________byte of data
1
BHE and _____ is used to select odd and even banks
A0
Primary function of memory interfacing is that the _________ should be able to read from and write into register
microprocessor
To perform any operations, the Mp should identify the __________
register
The Microprocessor places __________ address on the address bus
16 bit
The Microprocessor places 16 bit address on the add lines from that address by ______ register should be selected
one
The ________of the memory chip will identify and select the register for the EPROM
internal decoder
Microprocessor provides signal like ____ to indicate the read operation
MCMR
Group A comprises ____________
Port A and Port C Upper and Port B and Port C Lower
Control register is selected when A0 and A1 is
11
BSR mode is set When D7 is___________
0
Programmable peripheral input-output port is other name for _____.
parallel input-output port
Port C of 8255 can function independently as ___.
either input or output ports
All the functions of the ports of 8255 are achieved by programming the bits of an internal register called _________.
control word register
The data bus buffer is controlled by ______.
read/write control logic
The input provided by the microprocessor to the read/write control logic is _______.
all of the mentioned
Which mode is used for single handshake in 8255:
mode 1
Which chip is used for AD&DA converters to interface with 8086 processor __________.
8255
Parity error is to _____________.
Error if partity bit doesnot match in rx or tx
Over run error occurs ______________.
if Microprocessor fails to character loaded in receiver buffer
Framing error is __________
if stop bit is not detected
In mode word ASYN mode stop bit is used to ______
No of stop bits
In mode word 01 indicates ________
odd parity
In mode word 11 indicates ________
even parity
The registers that store the keyboard and display modes and operations programmed by CPU are
control and timing registers
The sensor RAM acts as 8-byte first-in-first-out RAM in
keyboard and strobed input mode
The registers that holds the address of the word currently being written by the CPU from the display RAM are
display address registers
When a key is pressed, a debounce logic comes into operation in
scanned keyboard mode with 2 key lockout
In keyboard/ Display mode set command to Encoded scan keyboard - 2 key lockout is _____.
0 0 0
Maximum size of the keyboard matrix is _______
8X8=64
NMI stands for
nonmaskable interrupt;
The register that stores all the interrupt requests in it in order to serve them one by one on priority basis is
Interrupt Request Register
The register that stores the bits required to mask the interrupt inputs is
Interrupt Mask register
. To complete a DMA transfer, a memory to memory transfer requires
a read-from and write-to memory cycle
ADC conversion involves
quantization
Traffic light signal is connected through
8255
Alarm controller is interfaced to 8086 using
8255, 8254
Which mode of 8254 is used for counter1 in alarm controller
mode 0
8255 is ______ pin IC.
24
8255 has _______ ports
3
In the I/O mode, the 8255 ports work as
programmable I/O ports
In BSR mode, only port C can be used to ___.
set and reset individual ports
The 8254 operating at ________ modes.
6
In 8254,Mode 1 is for__________
Hardware retriggerable one shot
In 8254,Mode 2 is for_________.
Rate generator
In 8254,Mode 3 is for _________-.
Square wave generator
UNIT 4
The architecture of 8051 consists of
all of the mentioned
A micro controller at-least should consist of:
CPU,RAM, ROM, I/O devices, serial and parallel ports and timers
8051 series has how many 16 bit registers?
2
When the micro controller executes some arithmetic operations, then the flag bits of which register are affected?
PSW
On power up, the 8051 uses which RAM locations for register R0- R7
00-07
8051 has ____ bit timers
16
8051 has an __________ number of external intrrupt sources
2
8051 has an __________ number of internal intrrupt sources
3
8051 has total number of register bank is ___
4
all the units of the 8051 communicate through an ____ bit internal data bus
8
B register is used for the operation ____
both b&c
PSW has about ___ flag and register
4
stack is an area of internal RAM address which act as ___________
LIFO
DPTR is used to fetch the data from ________ memory .
external
the 8051 access the external memory when EA pin is _______-
low
the 8051 provides ________- eight bit parallel I/O ports
4
in timer mode count rate is ______ of the oscillator frequency
{1/12}
8051 provides one serial port which can operate as _________
full duplex
8051 has an ____ chip clock osscilator
on
port 2 lines are used as a ____ order address lines
higher
8051 provides ___ROM
4KB
8051 provides_______ RAM withint the chip
128kb
8051 provides _____ external program and data memory
64KB
the internal memory can be accessed using an ___ bit address
8
the external memory can be accessed using an ___ bit address
16
The 128 bytes of internal RAM is divided into ____ blocks
3
the 8051 has four banking register with address ranging from ____________
00H-1FH
the address of individual bits range from _
00H-7FH
the memory space _______ is used as general purpose scratch pad memory .
30H-7EH
internal ROM th eaddress ranginf from _______-
0000H-0FFFH
the 8051 provides _____ of external data memory
64KB
the 8051 provides _____ of external program memory
64KB
The register that may be used as an operand register is
Accumulator and B register
The register that can be used as a scratch pad is
B register
The registers that contains the status information is
program status word
What is the address range of SFR Register bank?
80H-FFH
"Which pin of port 3 is has an alternative function as write control signal for
external data memory? "
P3.6
After reset, SP register is initialized to address________.
7H
TMOD is used to configure the _ 16bit timer
2
address of PCON is___H
87
The address fo TMOD register is _______.
89H
TH1 is ________.
Timer / Counter 1 High byte
The instruction, RLA performs
rotation of accumulator to left
The instruction, ADD A, #100 performs
100(decimal) is added to contents of accumulator
The instruction, ADD A, R7 is an example of
register instructions
The logical instruction that affect the carry flag during its execution is
RLC A;
The instruction that is used to complement or invert the bit of a bit addressable SFR is
CPL Bit
The mnemonic DJNZ stands for ___.
Decrement and Jump if not 0.
The other name for flag register
PSW
Find the CY and AC flag bits for the followinng codes MOV A, 0C2H ADD A, #3DH
CY= 1 & AC = 1
UNIT 5
How many bits are there in intel 8051 timer
16
What is the clock source for the timers?
from the crystal applied to the micro-controller
What is the frequency of the clock that is being used as the clock source for the timer?
controller’s crystal frequency /12
What is the function of the TMOD register?
TMOD register is used to set different timer’s or counter’s to their appropriate modes
TF1, TR1, TF0, TR0 bits are of which register?
TCON
"What is the Address (SFR) for TCON, SCON, SBUF, PCON and PSW
respectively?"
88H, 98H, 99H, 87H, 0D0H
Which special function register play a vital role in the timer/counter mode selection process by allocating the bits in it?
TMOD
Which bit must be set in TCON register in order to start the 'Timer 0' while operating in 'Mode 0'? TR0
The timer register is incremented once every osc/32 standard mode
FALSE
What is the bit transmitting or receiving capability of mode 1 in serial communication?
10bits
Which serial modes possess the potential to support the multi-processor type of communication?
Modes 2 & 3
Reception of the stop bit sets the _____ flag
R0
If ITO-IT1=0 ----> hardware interrupt are _____
level triggered
If ITO-IT1=1 ----> hardware interrupt are _____
edge triggered
When two interrupts occur simultaneously the ______________ priority interrupt will be serviced first.
higher
The interrupt priority are fixed by a __________ register
SFR
If a bit =0 in IP register the corresponding interrupt has a _____ priority
lower
full duplex mode allows data communication in ____ direction
both
In mode 1 , _____ is used to generate variable baud rate
timer 1
The common anode is connected to ___ supply
5v
All the key are open , _____ flag is set
zero
In keyboard interfacing,columns are connected to the the output port called ______
scan lines
In keyboard interfacing,To interface a set of key is to use _____ apporach
line per key
In keyboard interfacing,When key is pressed ,the port line has ___ voltage level
lower
In keyboard interfacing,To identify that which key is being pressed, we need to:
ground pins of the port one at a time
In keyboard interfacing,the spring action of the keys leads to ____ problem
key bounce
In keyboard interfacing,Multiple key press problem is commonly known as ______
rollover
D/A converters are generally
Binary ladder network
________________ is used as the multiplexed address/data bus
port 0
Which ports assist in addressing lower order and higher address bytes into the data bus simultaneously, while accessing the external data memory?
Port 0 & Port 2 respectively
A stepper motor is used that translates ___ into ____ movement
electric to mechanical
in stepper ____________ leads for stator winding
4
the _____ poles are detemined by the current sent through the wire coils
stator
The timer register is incremented once every______ standard mode
osc /12
For timer operation ,c/T = ___ in TMOD
0
For counter operation ,c/T = ____ in TMOD
1
Timer in the 8051 is used as _____ can be programmed to count pulses from external devicces
counter
Which of the following best describes the use of framing in asynchronous means of communication?
it tells us about the start and stop of the data to be transmitted or received
What is the function of SCON register?
to program the start bit, stop bit, and data bits of framing
The program access the memory location from __________ in the internal ROM
0000H-0FFFH
The ______ signal is used to activate output enable signal of the external ROM/EPROM to the _____ operation
read
The program access the memory location from __________ in the external ROM
1000H-FFFFH
"This statement will set the address of the bit to 1 (8051 Micro-controller):
SETB 01H"
FALSE
Data transfer from I/O to external data memory can only be done with the MOVX command.
TRUE
What happens when the RD signal becomes low during the read cycle?
Data byte gets loaded from external data memory to data bus
ADC chip is interfaced with the 8051 through the ____
8255 PPL
port 1 lines of the 8051 are connected to the __ line of the ADC
data
__ lines provides the control signal ALE,OE.
port 0
ADC chip can be directly interfaced with the 8051 _____ ports
parallel
Why two pins for ground are available in ADC0804?
for controlling the analog and the digital pins of the controller
Wow awesome
ReplyDeletePost a Comment